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quad, 1 6- bit, 125 msps, jesd204b 1.8 v analog - to - digital converter data sheet AD9656 features snr = 79.9 db fs at 16 mhz (v ref = 1.4 v) snr = 78.1 db fs at 64 mhz (v ref = 1.4 v) sfdr = 86 dbc to nyquist (v ref = 1.4 v) jesd204b subclass 1 coded serial digital outputs flexible analog input range : 2.0 v p - p to 2. 8 v p -p 1.8 v supply operation low p ower: 19 7 mw per channel at 125 msps ( two lane s) dnl = 0. 6 lsb (v ref = 1.4 v) inl = 4 .5 lsb (v ref = 1.4 v) 650 mhz analog input bandwidth, full power serial port control full chip and individual channel power - down modes built - in and custom digital test pattern generation multichip sync and clock divider standby mode applications medical i maging high s peed i maging quadrature radio receivers diversity radio receivers portable t est equipment functional block dia gram f igure 1. general description the AD9656 is a quad, 1 6- bit, 125 msps analog - to - digital converter (adc) with an on - chip sample - and - hold circuit designed for low cost, low power, small size, and ease of use. the device operates at a conversion rate of up to 125 msps and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. the adc requires a single 1.8 v power supply and lvpecl - / cmos - /lvds - compatible samp le rate clock for full performance operation. no external reference or driver components are required for many applications. individual channel power - down is supported and typically consumes less than 14 mw when all channels are disabled. the adc contains several features designed to maximize flexibility and minimize system cost, such as a programmable output clock , data alignment , and digital test pattern generation. the available digital test patterns include built - in deterministic and pseudorandom patter ns, along with custom user - defined test patterns entered via the serial port interface (spi). the AD9656 is available in a n rohs - compliant, nonmagnetic, 56- lead lfcsp. it is specified over the ?40c to +85c industrial temperature range. this product is protected by a u.s. patent. product highlights 1. it has a s mall f ootprint. four adcs are contained in a small, 8 mm 8 mm package. 2. an on - chip phase - locked loop ( pll ) allows users to provide a sin gle adc sampling clock; the pll multiplies the adc sampling clock to produce the corresponding jesd204b data rate clock. 3. the configurable jesd204b output block supports up to 6.4 gbps per lane. 4. jesd204b output block supports one , two , and four lane configurations . 5. low power of 198 mw per channel at 125 msps , two lane s. 6. t he spi control offers a wide range of flexible features to meet specific system requirements. AD9656 avdd pdwn dvdd drvdd ref select vi na? vi na+ vi nb? vi nb+ vi nd? vi nd+ vi nc? vi nc+ sense agnd sync vcm vref serdout0? serdout0+ dsysref+/ dsysref? clk+/ clk? csb sdio sclk rbias pipeline adc pipeline adc pipeline adc contro l registers jesd204b inter f ace high speed serializers cm l tx outputs clock management serial port inter f ace serdout1? serdout1+ serdout2? serdout2+ serdout3? serdout3+ dsync+ dsync? pipeline adc 16 16 16 16 svdd dvss 1v to 1.4v 1 1868-001 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. o ne technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com free datasheet http://
AD9656 data shee t table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 dc specifications, v ref = 1.4 v .................................................. 3 dc specifications, v ref = 1.0 v .................................................. 4 ac specifications, v ref = 1.4 v .................................................. 5 ac specifications, v ref = 1.0 v .................................................. 6 digital specifications ................................................................... 7 switching specifications .............................................................. 8 timing specifications .................................................................. 9 absolute maximum ratings .......................................................... 11 thermal resistance .................................................................... 11 esd caution ................................................................................ 11 pin configuration and function descriptions ........................... 12 typical performance characteristics ........................................... 14 v ref = 1.4 v ................................................................................. 14 v ref = 1.0 v ................................................................................. 17 equivalent circuits ......................................................................... 20 theory of operation ...................................................................... 21 analog input considerations ................................................... 21 voltage reference ....................................................................... 23 clock input considerations ...................................................... 24 power dissipation and power - down mode ........................... 26 digital outputs ........................................................................... 27 serial po rt interface (spi) .............................................................. 33 configuration using the spi ..................................................... 33 hardware interface ..................................................................... 33 spi accessible features .............................................................. 34 memory map .................................................................................. 35 reading the memory map register table ............................... 35 memory map register table ..................................................... 36 memory map register descriptions ........................................ 40 applications information .............................................................. 42 d esign guidelines ...................................................................... 42 power and ground recommendations ................................... 42 clock stability considerations ................................................. 42 exposed pad thermal heat slug recommendations ............ 42 referen ce decoupling ................................................................ 42 spi port ........................................................................................ 42 o utline d imensions ....................................................................... 43 ordering guide .......................................................................... 43 revision hi story 1 2 /13 revision 0: initial version rev. 0 | page 2 of 44 free datasheet http://
data sheet AD9656 specifications dc specifications , v ref = 1.4 v avdd = 1.8 v, drvdd = 1.8 v, 2.8 v p - p full - scale differential input, 1.4 v reference, a in = ?1.0 dbfs, unless otherwise noted. table 1 . parameter 1 temperature min typ max unit resolution 16 bits accuracy no missing codes 25c guaranteed offset error 25c ?0.1 +0.14 +0.5 % fsr offset matching 25c 0 0.1 0.4 % fsr gain error 25c ? 1.0 +1.0 +3.1 % fsr gain matching 25c 0 1.1 2.0 % fsr differential nonlinearity (dnl) 25c ?0.95 0. 6 +2.54 lsb integral nonlinearity (inl) 25c ?10.0 4.5 +10.0 lsb temperature drift gain error full 6.1 ppm/ c offset error full ? 2 ppm/ c internal voltage reference output voltage 25c 1.37 1. 4 1.41 v load regulation at 1.0 ma 25c 4 mv input resistance 25c 7.5 k input - referred noise v ref = 1. 4 v 25c 2.1 lsb rms analog inputs differential input voltage 25c 2.8 v p -p common - mode voltage 25c 0.9 v common - mode range 25c 0.7 1.1 v differential input resistance 25c 2.6 k differential input capacitance 25c 7 pf power supply avdd 25c 1.7 1.8 1.9 v dvdd, drvdd 25c 1.7 1.8 1.9 v i avdd ( 125 msps, two lane s ) 2 25c 2 88 306 ma i dvdd ( 125 msps, two lane s ) 2 25c 67 72 ma i drvdd ( 125 msps, two lane s ) 2 25c 83 88 ma total power consumption dc input ( 125 msps, four channels onto two lane s ) 25c 706 mw sine wave input ( 125 msps, four channels onto two lane s ) 2 25c 788 839 mw power - down mode 25c 14 mw standby mode 3 25c 547 mw 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 measured with a low input frequency, full - scale sine wave on all four channels. 3 standby c an be controlled via the spi. rev. 0 | page 3 of 44 free datasheet http://
AD9656 data shee t dc specifications , v ref = 1.0 v avdd = 1.8 v, drvdd = 1.8 v, 2.0 v p - p full - scale differential input, 1.0 v reference, a in = ?1.0 dbfs, unless otherwise noted. table 2 . parameter 1 temperature min typ max unit resolution 16 bits accuracy no missing codes 25c guaranteed offset error 25c 0. 2 % fsr offset matching 25c 0.13 % fsr gain error 25c 1.0 % fsr gain matching 25c 0.4 % fsr differential nonlinearity (dnl) 25c 0. 6 lsb integral nonlinearity (inl) 25c 6 . 0 lsb temperature drift gain error full 3.1 ppm/c offset error full ? 3 ppm/c internal voltage reference output voltage 25c 1. 0 v load regulation at 1.0 ma 25c 2 mv input resistance 25c 7.5 k input - referred noise v ref = 1. 0 v 25c 2. 7 lsb rms analog inputs differential input voltage 25c 2. 0 v p - p common - mode voltage 25c 0.9 v common - mode range 25c 0.5 1.3 v differential input resistance 25c 2.6 k differential input capacitance 25 c 7 pf power supply avdd 25c 1.7 1.8 1.9 v dvdd, drvdd 25c 1.7 1.8 1.9 v i avdd ( 125 msps , two lane s ) 2 25c 276 ma i dvdd ( 125 msps , two lane s ) 2 25c 69 ma i drvdd ( 125 msps , two lane s ) 2 25c 83 ma total power consumption dc input ( 125 msps , four channels onto two lane s ) 25c 688 mw sine wave input ( 125 msps , four channels onto two lane s ) 25c 771 mw power - down mode 25c 14 mw standby mode 3 25c 520 mw 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 measured with a low input frequency, full - scale si ne wave on all four channels. 3 standby can be controlled via the spi. rev. 0 | page 4 of 44 free datasheet http://
data sheet AD9656 ac specifications , v ref = 1.4 v avdd = 1.8 v, drvdd = 1.8 v, 2.8 v p - p full - scale differential input, 1.4 v reference, a in = ?1.0 dbfs, unless otherwise noted. table 3 . parameter 1 temperature min typ max unit signal -to - noise ratio (snr) f in = 9.7 mhz 25c 80. 1 dbfs f in = 16 mhz 25c 79.9 dbfs f in = 64 mhz 25c 75.7 78.1 dbfs f in = 1 28 mhz 25c 75 dbfs f in = 201 mhz 25c 72.7 dbfs f in = 301 mhz 25c 69.7 dbfs signal -to - noise - and - distortion (sinad) ratio f in = 9.7 mhz 25c 79.6 dbfs f in = 16 mhz 25c 7 8.4 dbfs f in = 64 mhz 25c 74.8 77.3 dbfs f in = 1 28 mhz 25c 74.4 dbfs f in = 201 mhz 25c 71 dbfs f in = 301 mhz 25c 68.6 dbfs effective number of bits (enob) f in = 9.7 mhz 25c 12.9 bits f in = 16 mhz 25c 12. 7 bits f in = 64 mhz 25c 12.1 12. 5 bits f in = 1 28 mhz 25c 12.1 bits f in = 201 mhz 25c 11.5 bits f in = 301 mhz 25c 11.1 bits spurious - free dynamic range (sfdr) f in = 9.7 mhz 25c 8 9 dbc f in = 16 mhz 25c 87 dbc f in = 64 mhz 25c 78 86 dbc f in = 1 28 mhz 25c 84 dbc f in = 201 mhz 25c 76 dbc f in = 301 mhz 25c 75 dbc worst harmonic (second or third) f in = 9.7 mhz 25c ? 8 9 dbc f in = 16 mhz 25c ? 87 dbc f in = 64 mhz 25c ? 86 ? 78 dbc f in = 1 28 mhz 25c ? 84 dbc f in = 201 mhz 25c ? 76 dbc f in = 301 mhz 25c ? 75 dbc worst other harmonic (excluding second or third) f in = 9.7 mhz 25c ? 9 6 dbc f in = 16 mhz 25c ? 92 dbc f in = 64 mhz 25c ? 90 ? 87 dbc f in = 1 28 mhz 25c ? 89 dbc f in = 201 mhz 25c ? 93 dbc f in = 301 mhz 25c ? 90 dbc two - tone intermodulation distortion (imd) input amplitude = ? 7.0 dbfs f in1 = 70.5 mhz, f in2 = 72.5 mhz 25c ? 84 dbc rev. 0 | page 5 of 44 free datasheet http://
AD9656 data shee t parameter 1 temperature min typ max unit crosstalk 2 25c ? 9 3 db crosstalk (overrange condition) 3 25c ? 89 db analog input bandwidth, full power 25c 650 mhz 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 crosstalk is measured at 70 mhz with ?1.0 dbfs analog input on one channel and no input on the adjacent channel. 3 overrange condition is defined as the input being 3 db above full scale . ac specifications , v ref = 1. 0 v avdd = 1.8 v, drvdd = 1.8 v, 2.0 v p - p full - scale differential input, 1.0 v reference, a in = ?1.0 dbfs, unless otherwise noted. table 4 . parameter 1 temperature min typ max unit signal -to - noise ratio (snr) f in = 9.7 mhz 25c 78 dbfs f in = 16 mhz 25c 77. 9 dbfs f in = 64 mhz 25c 76. 8 dbfs f in = 1 28 mhz 25c 74.3 dbfs f in = 20 1 mhz 25c 72.1 dbfs f in = 301 mhz 25c 69.3 dbfs signal -to - noise - and - distortion (sinad) ratio f in = 9.7 mhz 25c 78 dbfs f in = 16 mhz 25c 77.7 dbfs f in = 64 mhz 25c 76.1 dbfs f in = 1 28 mhz 25c 74 dbfs f in = 201 mhz 25c 71.1 dbfs f in = 301 mhz 25c 68.6 dbfs effective number of bits (enob) f in = 9.7 mhz 25c 12.7 bits f in = 16 mhz 25c 12.6 bits f in = 64 mhz 25c 12.3 bits f in = 1 28 mhz 25c 12.0 bits f in = 20 1 mhz 25c 11.5 bits f in = 301 mhz 25c 11.1 bits spurious - free dynamic range (sfdr) f in = 9.7 mhz 25c 9 9 dbc f in = 16 mhz 25c 92 dbc f in = 64 mhz 25c 89 dbc f in = 1 28 mhz 25c 87 dbc f in = 20 1 mhz 25c 78 dbc f in = 301 mhz 25c 78 dbc worst harmonic (second or third) f in = 9.7 mhz 25c ? 9 9 dbc f in = 16 mhz 25c ? 92 dbc f in = 64 mhz 25c ? 89 dbc f in = 1 28 mhz 25c ? 87 dbc f in = 20 1 mhz 25c ? 78 dbc f in = 301 mhz 25c ? 78 dbc worst other harmonic (excluding second or third) f in = 9.7 mhz 25c ? 95 dbc f in = 16 mhz 25c ? 95 dbc f in = 64 mhz 25c ? 94 dbc f in = 1 28 mhz 25c ? 89 dbc f in = 20 1 mhz 25c ? 91 dbc f in = 301 mhz 25c ? 89 dbc rev. 0 | page 6 of 44 free datasheet http://
data sheet AD9656 parameter 1 temperature min typ max unit two - tone intermodulation distortion (imd) input amplitude = ?7.0 dbfs f in1 = 70.5 mhz, f in2 = 72.5 mhz 25c ? 89 dbc crosstalk 2 25c ? 9 4 db crosstalk (overrange condition) 3 25c ? 89 db analog input bandwidth, full power 25c 650 mhz 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 crosstalk is measured at 70 mhz with ? 1.0 dbfs analog input on one channel and no input on the adjacent channel. 3 overrange condition is defined as the input being 3 db above full - scale. digital specificatio ns avdd = 1.8 v, drvdd = 1.8 v, 2 .8 v p - p differential input, 1. 4 v reference , a in = ?1.0 dbfs, unless otherwise noted. table 5 . parameter 1 temperature min typ max unit clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl differential input voltage range 2 full 0.2 3.6 v p -p input voltage range full agnd ? 0. 2 avdd + 0.2 v input common - mode voltage full 0.9 v input resistance (differential) 25c 15 k input capacitance 25c 4 pf d sync input ( d sync + / d sync ? ) logic compliance lvds internal common - mode bias full 0.9 v differential input voltage range full 0.3 3.6 v p - p input voltage range full dgnd dvdd v input common - mode voltage range full 0.9 1.4 v high level input current full ?5 +5 a low level input current full ?5 +5 a input capacitance full 1 pf input resistance full 12 16 20 k d sysref input ( d sysref +/dsysref? ) logic compliance lvds internal common - mode bias full 0.9 v differential input voltage range full 0.3 3.6 v p - p input voltage range full agnd avdd v input common - mode voltage range full 0.9 1.4 v high level input current full ?5 +5 a low level input current full ?5 +5 a input capacitance full 4 pf input resistance full 8 10 12 k logic inputs (pdwn, sync, sclk) logic 1 voltage range full 1.2 avdd + 0. 2 v logic 0 voltage range full 0 0.8 v input resistance 25c 30 k input capacitance 25c 2 pf logic input ( csb ) logic 1 voltage range full 1.2 avdd + 0.2 v logic 0 voltage range full 0 0.8 v input resistance 25c 26 k input capacitance 25c 2 pf rev. 0 | page 7 of 44 free datasheet http://
AD9656 data shee t parameter 1 temperature min typ max unit logic input (sdio) logic 1 voltage range full 1.2 avdd + 0. 2 v logic 0 voltage range full 0 0.8 v input resistance 25c 26 k input capacitance 25c 5 pf logic output (sdio) 3 logic 1 voltage (i oh = 800 a) full 1.79 v logic 0 voltage (i ol = 50 a) full 0.05 v digital outputs ( serdoutx+, serdoutx?) logic compliance full cml differential output voltage (v od ) full 400 600 750 mv output offset voltage (v os ) full 0.75 drvdd/2 1.05 v 1 see the an - 835 application note , understan ding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 s pecified for lvds and lvpecl only. 3 s pecified for the sdio pins on 13 individual AD9656 devices sharing the same connection. switching specificat ions avdd = 1.8 v, drvdd = 1.8 v, 2 .8 v p - p differential input, 1. 4 v reference, a in = ?1.0 dbfs, unless otherwise noted. table 6 . parameter 1 , 2 temperature min typ max unit clock 3 input clock rate full 40 1000 mhz conversion rate full 40 125 msps clock pulse width high (t eh ) full 4.00 ns clock pulse width low (t el ) full 4.00 ns sync setup time to clock full 1.4 ns sync hold time to clock full ? 0.4 ns dsysref setup time to clock ( t refs ) 4 full 370 600 ps dsysref hold time to clock ( t ref h ) 4 full ? 92 0 ps data output parameters data output period or unit interval (ui) full l/(20 m f s ) seconds data output duty cycle 25c 50 % data valid time 25c 0.8 1 ui pll lock time (t lock ) 25c 25 s wake - up time standby 25c 250 ns adc (power - down) 5 25c 375 s output (power - down) 6 25c 50 s d sync falling edge to first k.28 characters full 4 multiframes cgs phase k.28 characters duration full 1 multiframe pipeline delay jesd204b m 4 , l1 mode (latency) full 23 cycles 7 jesd204b m 4 , l2 mode (latency) full 29 cycles 7 jesd204b m 4 , l 4 mode (latency) full 44 cycles 7 data rate per lane full 6.4 gbps deterministic jitter (d j ) at 6.4 gbps full 8 ps random jitter (r j ) at 6.4 gbps full 1.25 ps rms output rise time/fall time full 50 ps differential termination resistance 25c 100 rev. 0 | page 8 of 44 free datasheet http://
data sheet AD9656 parameter 1 , 2 temperature min typ max unit aperture aperture delay (t a ) 25c 1 ns aperture uncertainty (jitter, t j ) 25c 135 fs rms out -of - range recovery time 25c 1 clock cycles 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed . 2 measured on standard fr - 4 material. 3 the clock c an be adjusted via the spi. the conversion rate is the clock rate after the divider. 4 refer to figure 3 for timing diagram. 5 time required for the adc to return to normal operation from power - down mode. 6 time required for the jesd204b output to return to normal operation from power - down mode. 7 adc conversion rate cycles. timing specification s table 7 . parameter description limit unit spi timing requirements see figure 70 t ds setup time between the data and the rising edge of sclk 2 ns min t dh hold time between the data and the rising edge of sclk 2 ns min t clk period of the sclk 40 ns min t s setup time between csb and sclk 2 ns min t h hold time between csb and sclk 2 ns min t high sclk pulse width high 10 ns min t low sclk pulse width low 10 ns min t en_sdio time required for the sdio pin to switch from an input to an output relative to the sclk falling edge (not shown in figure ) 10 ns min t dis_sdio time required for the sdio pin to switch from an output to an input relative to the sclk rising edge (not shown in figure ) 10 ns min rev. 0 | page 9 of 44 free datasheet http://
AD9656 data shee t timing diagrams refer to the memory map register table section for spi register settings. figure 2 . data output timing figure 3 . dsysref +/dsysref? setup and hold timing ( clock divider = 1) vina+/ vina? vinb+/ vinb? vinc+/ vinc? vind+/ vind? clk+ clk? serdoutx+ clk+ clk? serdoutx? vinb, sample n ? 23, msb firs t , 8b/10b encoded d at a vinc, sample n ? 23, msb firs t , 8b/10b encoded d at a vind, sample n ? 23, msb firs t , 8b/10b encoded d at a vina, sample n ? 23, msb firs t , 8b/10b encoded d at a sample n n ? 23 n ? 21 n ? 22 n + 1 n ? 1 n ? 20 sample n n ? 23 n ? 21 n ? 22 n + 1 n ? 1 n ? 20 sample n n ? 23 n ? 21 n ? 22 n + 1 n ? 1 n ? 20 sample n n ? 23 n ? 21 n ? 22 n + 1 n ? 1 n ? 20 n ? 19 n ? 19 n ? 19 n ? 19 1 1868-002 t refs clk+ clk? dsysref? dsysref+ t refh 1 1868-003 rev. 0 | page 10 of 44 free datasheet http://
data sheet AD9656 absolute maximum rat ings table 8 . parameter rating electrical avdd to agnd ?0.3 v to +2.0 v drvdd to agnd ?0.3 v to +2.0 v dvdd to dvss ?0.3 v to +2.0 v svdd to agnd ?0.3 v to +2.0 v digital outputs to agnd ?0.3 v to +2.0 v clk+, clk? to agnd ?0.3 v to +2.0 v v in x+, v in x ? to agnd ?0.3 v to +2.0 v d sysref+, d sysref ? to agnd ?0.3 v to +2.0 v dsync ? , dsync + to agnd ?0.3 v to +2.0 v sclk, sdio, csb , pdwn to agnd ?0.3 v to + 3.9 v sync to agnd ?0.3 v to +2.0 v rbias to agnd ?0.3 v to +2.0 v vcm, vref, sense to agnd ?0.3 v to +2.0 v environmental operating temperature range (ambient) ?40 c to +85 c maximum junction temperature 150c lead temperature (soldering, 10 sec) 300c storage temperature range (ambient) ?65 c to +150 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is for a 4 - layer printed circuit board (pcb) wi th solid ground plane (simulated). the e xposed pad is soldered to the pcb ground . table 9 . thermal resistance package type air flow velocity (m/sec) ja (c/w) jb (c/w) 1 jc top (c/w) 1 jc bottom (c/w) 1 56 - lead l f c s p, 8 mm 8 mm 0 22.4 7.7 7.42 2.29 1 19.0 n/a n/a n/a 2.5 17.6 n/a n/a n/a 1 n/a = not applicable. esd caution rev. 0 | page 11 of 44 free datasheet http://
AD9656 data shee t pin configuration an d function descripti ons figure 4. pin configuration, top view table 10 . pin function descriptions pin no. mnemonic description 0 agnd , exposed pad analog ground , exposed pad. the exposed thermal pad on the bottom of the package provides the analog ground for the device . this exposed pad must be connected to ground for proper operation. 1, 4, 5 , 8, 11, 39, 42 , 43, 46, 52, 53, 56 avdd 1.8 v analog supply pins. 2 v in d + adc d analog input true . 3 v in d ? adc d analog input complement. 6, 7 clk ? , clk+ differential encode clock. pecl, lvds, or 1.8 v cmos inputs . 9 dsysref+ active low jesd204b lvds sysref input true . 10 dsysref ? active low jesd204b lvds sysref input complement. 12, 32 dvdd digital supply . 13, 31 dvss digital g round . 14, 15, 29, 30 n i c no t internally connect ed . can be connected to ground if desired. 16 dsync + active low jesd204b lvds sync input true . 17 dsync ? active low jesd204b lvds sync input complement. 18, 23, 28 drvdd digital output driver supply. 19 ser dout 3 ? lane 3 digital output complement. 20 ser dout 3 + lane 3 digital output true. 21 ser dout 2 + lane 2 digital output true. 22 ser dout 2 ? lane 2 digital output complement. 24 ser dout 1 ? lane 1 digital output complement. 25 ser dout 1 + lane 1 digital output true. 26 ser dout 0 + lane 0 digital output true. 27 ser dout 0 ? lane 0 digital output complement. 33 svdd spi supply pin . notes 1. nic = not internal l y connected. can be connected to ground if desired. 2. dnc = do not connect. do not connect to this pin. 3. the exposed therma l p ad on the bot t om of the p ackage provides the analog ground for the p ar t . this exposed p ad must be connected t o ground for proper oper a tion. 15 16 17 18 19 20 21 22 23 24 25 26 27 28 nic dsync+ dsync? dr vdd serdout3? serdout3+ serdout2+ serdout2? dr vdd serdout1? serdout1+ serdout0+ serdout0? dr vdd 56 55 54 53 52 51 50 49 a vdd vinc+ vinc? a vdd a vdd sync vcm vref 48 47 46 45 sense rbias a vdd vinb? 44 43 vinb+ a vdd 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 a vdd vind+ vind? a vdd a vdd clk? clk+ a vdd dsysref+ dsysref? a vdd dvdd dvss nic a vdd vina+ vina? a vdd pdwn csb sdio sclk dnc svdd dvdd dvss nic nic 42 41 40 39 38 37 36 35 34 33 32 31 30 29 t op view AD9656 1 1868-004 rev. 0 | page 12 of 44 free datasheet http://
data sheet AD9656 pin no. mnemonic description 34 dnc do not connect . do not connect to this pin . 35 sclk spi clock input . 36 sdio spi data input and output , bidirectional . 37 csb spi chip select bar. active low enable; 30 k internal pull -up resistor . 38 pdwn digital input . this pin has a 30 k internal pull - down resistor . pdwn high = power - down device , and pdwn low = run device ( normal operation ) . 40 v ina? adc a analog input complement. 41 v ina+ adc a analog input true. 44 v inb+ adc b analog input true. 45 v inb? adc b analog input complement. 47 rbias sets analog current bias. this pin c onnect s a 10 k (1% tolerance) resistor to ground. 48 sense reference mode selection. 49 vref voltage reference input and output. 50 vcm analog input common - mode voltage. 51 sync digital input. s ynchronous input to clock divider. 54 v inc? adc c analog input complement. 55 v inc+ adc c analog input true. rev. 0 | page 13 of 44 free datasheet http://
AD9656 data shee t typical performance characteristics v ref = 1.4 v figure 5 . single- tone 32k fft with f in = 9.7 mhz, f sample = 125 msps, v ref = 1.4 v figure 6 . single- tone 32k fft with f in = 16.3 mhz, f sample = 125 msps , v ref = 1.4 v figure 7 . single- tone 32k fft with f in = 64 mhz, f sample = 125 msps, v ref = 1.4 v figure 8. single - tone 32k fft with f in = 128.1 mhz , f sample = 125 msps, v ref = 1.4 v figure 9 . single- tone 32k fft with f in = 201 mhz, f sample = 125 msps, v ref = 1.4 v figure 10 . single - tone 32k fft with f in = 301 mhz, f sample = 12 5 msps , v ref = 1.4 v ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 20 40 60 amplitude (dbfs) frequenc y (mhz) a in = ?1dbfs f in = 9.7mhz snr = 80.1dbfs sinad = 78.7dbfs sfdr = 92dbc 1 1868-038 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 20 40 60 amplitude (dbfs) frequenc y (mhz) a in = ?1dbfs f in = 16.3mhz snr = 79.9dbfs sinad = 78.3dbfs sfdr = 89dbc 1 1868-037 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 20 40 60 amplitude (dbfs) frequenc y (mhz) a in = ?1dbfs f in = 64mhz snr = 78.5dbfs sinad = 76.4dbfs sfdr = 83dbc 1 1868-036 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 20 40 60 amplitude (dbfs) frequenc y (mhz) a in = ?1dbfs f in = 128.1mhz snr = 75.3dbfs sinad = 73.3dbfs sfdr = 81dbc 1 1868-034 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 20 40 60 amplitude (dbfs) frequenc y (mhz) 1 1868-033 a in = ?1dbfs f in = 201mhz snr = 72.6dbfs sinad = 70.2 dbfs sfdr = 76dbc ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 20 40 60 amplitude (dbfs) frequenc y (mhz) a in = ?1dbfs f in = 301mhz snr = 69.8dbfs sinad = 67.5dbfs sfdr = 74dbc 1 1868-032 rev. 0 | page 14 of 44 free datasheet http://
data sheet AD9656 figure 11 . snr/sfdr vs. input amplitude (a in ), f in = 9.7 mhz, f sample = 125 msps, v ref = 1.4 v figure 12 . two - tone 32k fft with f in1 = 70.5 mhz and f in2 = 72.5 mhz, f sample = 125 msps, v ref = 1.4 v figure 13 . two - tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 70.5 mhz and f in2 = 72.5 mhz, f sample = 125 msps, v ref = 1.4 v figure 14 . snr/sfdr vs. input frequency (f in ), f sample = 125 msps , v ref = 1.4 v figure 15 . snr/sfdr vs. temperature, f in = 9.7 mhz, f sample = 125 msps, v ref = 1.4 v figure 16 . in tegral nonlinearity (inl), f in = 9.7 mhz, f sample = 125 msps, v ref = 1.4 v ?20 0 20 40 60 80 100 120 ?100 ?80 ?60 ?40 ?20 0 snr/sfdr (dbfs/dbc) input amplitude (dbfs) sfdr (dbfs) snr (dbfs) sfdr (dbc) snr (db) 1 1868-030 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 20 40 60 amplitude (dbfs) frequenc y (mhz) f2 ? f1 a in = ?7dbfs f in1 = 70.5mhz f in2 = 72.5mhz imd2 = ?98dbc imd3 = ?84dbc sfdr = 84dbc f1 + f2 f1 + 2f2 2f1 + f2 2f2 ? f1 2f1 ? f2 1 1868-035 ?120 ?100 ?80 ?60 ?40 ?20 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 sfdr/imd3 (dbc/dbfs) input amplitude (dbfs) imd3 (dbc) ?sfdr (dbc) ?sfdr (dbfs) imd3 (dbfs) 1 1868-027 0 10 20 30 40 50 60 70 80 90 100 0 50 100 150 200 250 300 350 400 450 500 snr/sfdr (dbfs/dbc) input frequenc y (mhz) 1 1868-025 sfdr (dbc) snr (dbfs) 60 70 80 90 100 1 10 ?40 ?20 0 20 40 60 80 snr/sfdr (dbfs/dbc) temper a ture (c) snr (dbfs) sfdr (dbc) 1 1868-023 ?6 ?4 ?2 0 2 4 6 0 10000 20000 30000 40000 50000 60000 in l (lsb) output code 1 1868-015 rev. 0 | page 15 of 44 free datasheet http://
AD9656 data shee t figure 17 . differential nonlinearity (dnl), f in = 9.7 mhz, f sample = 125 msps, v ref = 1.4 v figure 18 . input referred noise histogram, f sample = 125 msps, v ref = 1.4 v figure 19 . snr/sfdr vs. sample rate, f in = 9.7 mhz, v ref = 1.4 v figure 20 . snr/sfdr vs. sample rate, f in = 64 mhz , v ref = 1.4 v ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0 10000 20000 30000 40000 50000 60000 dn l (lsb) output code 1 1868-016 0 50000 100000 150000 200000 250000 300000 350000 400000 450000 n ? 10 n ? 9 n ? 8 n ? 7 n ? 6 n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 number of hits output code 2.0 lsb rms 1 1868-021 0 20 40 60 80 100 120 40 60 80 100 120 snr/sfdr (dbfs/dbc) sample r a te (msps) sfdr (dbc) snr (dbfs) 1 1868-019 0 20 40 60 80 100 120 40 50 60 70 80 90 100 1 10 120 snr/sfdr (dbfs/dbc) sample r a te (msps) sfdr (dbc) snr (dbfs) 1 1868-017 rev. 0 | page 16 of 44 free datasheet http://
data sheet AD9656 v ref = 1.0 v figure 21 . single - tone 32k fft with f in = 9.7 mhz, f sample = 125 msps, v ref = 1.0 v figure 22 . single - tone 32k fft with f in = 16.3 mh z , f sample = 125 msps , v ref = 1.0 v figure 23 . single - tone 32k fft with f in = 64 mhz, f sample = 125 msps, v ref = 1.0 v figure 24 . single - tone 32k fft with f in = 128 .1 mhz , f sample = 125 msps, v ref = 1.0 v figure 25 . single - tone 32k fft with f in = 201 mhz, f sample = 125 msps, v ref = 1.0 v figure 26 . single - tone 32k fft with f in = 301 mhz , f sample = 1 25 msps , v ref = 1.0 v ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 20 40 60 amplitude (dbfs) frequenc y (mhz) a in = ?1dbfs f in = 9.7mhz snr = 78.0dbfs sinad = 77.0dbfs sfdr = 99dbc 1 1868-145 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 20 40 60 amplitude (dbfs) frequenc y (mhz) 1 1868-143 a in = ?1dbfs f in = 16.3mhz snr = 78.0dbfs sinad = 76.8dbfs sfdr = 94dbc ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 20 40 60 amplitude (dbfs) frequenc y (mhz) a in = ?1dbfs f in = 64mhz snr = 76.9dbfs sinad = 75.7dbfs sfdr = 90dbc 1 1868-149 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 20 40 60 amplitude (dbfs) frequenc y (mhz) a in = ?1dbfs f in = 128.1mhz snr = 74.5dbfs sinad = 73.0dbfs sfdr = 84dbc 1 1868-041 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 20 40 60 amplitude (dbfs) frequenc y (mhz) a in = ?1dbfs f in = 201mhz snr = 72.2dbfs sinad = 70.2dbfs sfdr = 78dbc 1 1868-040 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 20 40 60 amplitude (dbfs) frequenc y (mhz) a in = ?1dbfs f in = 301mhz snr = 69.3dbfs sinad = 67.6dbfs sfdr = 77dbc 1 1868-039 rev. 0 | page 17 of 44 free datasheet http://
AD9656 data shee t figure 27 . snr/sfdr vs. input amplitude (a in ), f in = 9.7 mhz, f sample = 125 msps, v ref = 1.0 v figure 28 . two - tone 32k fft with f in1 = 70.5 mhz and f in2 = 72.5 mhz, f sample = 125 msps, v ref = 1.0 v figure 29 . two - tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 70.5 mhz and f in2 = 72.5 mhz, f sample = 125 msps, v ref = 1.0 v figure 30 . snr/sfdr vs. input frequency (f in ), f sample = 125 msps , v ref = 1.0 v figure 31 . snr/sfdr vs. temperature, f in = 9.7 mhz, f sample = 125 msps, v ref = 1.0 v figure 32 . integral nonlinearity ( inl ), f in = 9.7 mhz, f sample = 125 msps, v ref = 1.0 v ?20 0 20 40 60 80 100 120 ?90 ?70 ?50 ?30 ?10 snr/sfdr (dbfs/dbc) input amplitude (dbfs) sfdr (dbfs) snr (dbfs) sfdr (dbc) snr (db) 1 1868-031 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 20 40 amplitude (dbfs) frequenc y (mhz) f2 ? f1 a in = ?7dbfs f in1 = 70.5mhz f in2 = 72.5mhz imd2= ?99dbc imd3 = ?89dbc sfdr = 89dbc f1 + f2 f1 + 2f2 2f1 + f2 2f2 ? f1 2f1 ? f2 1 1868-029 ?120 ?100 ?80 ?60 ?40 ?20 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 sfdr/imd3 (dbc/dbfs) input amplitude (dbfs) ?sfdr (dbc) imd3 (dbc) ?sfdr (dbfs) imd3 (dbfs) 1 1868-028 0 10 20 30 40 50 60 70 80 90 100 1 10 0 50 100 150 200 250 300 350 400 450 500 snr/sfdr (dbfs/dbc) input frequenc y (mhz) snr (dbfs) sfdr (dbc) 1 1868-026 60 70 80 90 100 1 10 ?40 ?20 0 20 40 60 80 snr/sfdr (dbfs/dbc) temper a ture (c) snr (dbfs) sfdr (dbc) 1 1868-024 ?6 ?4 ?2 0 2 4 6 0 10000 20000 30000 40000 50000 60000 in l (lsb) output code 1 1868-009 rev. 0 | page 18 of 44 free datasheet http://
data sheet AD9656 figure 33 . differential nonlinearity ( dnl ), f in = 9.7 mhz, f sample = 125 msps, v ref = 1.0 v figure 34 . input referred noise histogram, f sample = 125 msps, v ref = 1.0 v figure 35 . snr/sfdr vs. sample rate, f in = 9.7 mhz, v ref = 1.0 v figure 36 . snr/sfdr vs. sample rate, f in = 64 mhz , v ref = 1.0 v ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0 10000 20000 30000 40000 50000 60000 dn l (lsb) output code 1 1868-010 0 50000 100000 150000 200000 250000 300000 350000 number of hits output code 2.0 lsb rms 2.7 lsb rms n ? 12 n ? 10 n ? 8 n ? 6 n ? 4 n ? 2 n n + 2 n + 4 n + 6 n + 8 n + 10 n + 12 1 1868-022 0 20 40 60 80 100 120 40 50 60 70 80 90 100 1 10 120 snr/sfdr (dbfs/dbc) sample r a te (msps) snr (dbfs) sfdr (dbc) 1 1868-020 0 20 40 60 80 100 120 40 50 60 70 80 90 100 1 10 120 snr/sfdr (dbfs/dbc) sample r a te (msps) sfdr (dbc) snr (dbfs) 1 1868-018 rev. 0 | page 19 of 44 free datasheet http://
AD9656 data shee t equivalent cir cuits figure 37 . equivalent analog input circuit figure 38 . equivalent clock input circuit figure 39 . equivalent sdio input circuit figure 40 . equivalent serdoutx circuit figure 41 . equivalent sclk, sync, and pdwn input circuit figure 42 . equivalent rbias and vcm circuit figure 43 . equivalent csb input circuit figure 44 . equivalent vref circuit a vdd vinx 1 1868-043 clk+ clk? 0.9v 15k? 10? 10? 15k? a vdd a vdd 1 1868-044 31k? sdio 400? a vdd 1 1868-045 dr vdd serdoutx? serdoutx+ dr vdd r term dr vdd v cm 3m a 3m a 6m a 1 1868-148 350? a vdd 30k? sclk, sync, and pdwn 1 1868-047 rbias and vcm 375? a vdd 1 1868-048 csb 350? a vdd 30k? 1 1868-049 a vdd 350? 7.5? 1 1868-050 vref rev. 0 | page 20 of 44 free datasheet http://
data sheet AD9656 theory of operation the AD9656 is a multistage, pipelined adc . each stage provides sufficient overlap to correct for flash errors in the preceding stage. the quantized outputs from each stage are combined into a final 1 6 - bit result in the digital correction logic. the serializer transm its this converted data in a 16 - bit output. the pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with the preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched - capacitor dac and an interstage residue amplifier (for example, a multiplying digital - to - analog converter [ mdac ] ). the residue amplifier magnifies the differen ce between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the output staging block aligns the data, corrects errors, and passes the data to the output buffers. the data is then serialized and aligned to the frame and data clocks. analog input conside rations the analog input to the AD9656 is a differential switched - capacitor circuit designed for processing differential input signals. this circuit can support a wide common - mode range while maintaining excellent performance. by using an input common - mode voltage of midsupply, users can minimize signal - dependent errors and achieve optimum performance. figure 45 . switched - capacitor input circuit the clock signal alternately switches the input circuit between sample mode and hold mode (see figure 45 ). when the input circuit is switched to sample mode, the signal source must be capable of charging the sample capacitors and settling within one - half of a clock cycle. a small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. in addition, low q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and therefore achieve the maximum bandwidth of the adc. such use of low q inductors or ferrite beads is required when driving the converter front end at high if frequencies. either a differential capacitor or t wo single - ended capacitors can be placed on the inputs to provide a matching passive network. this ultimately creates a low - pass filter at the input to limit unwanted broadband noise. see the an - 7 42 application note , the an - 827 application note , and the analog dialogue article transformer - coupled f ront - end for wideband a/d converters for more information . in general, the precise values depend on the application. input common - mode voltage the analog inputs of the AD9656 are not internally d c - biased. therefore, in ac - coupled applications, the user must provide this bias externally. setting the device so that v cm = av dd /2 is recommended for optimum performance, but the device can function over a wider v cm range with reasonable performance, as shown in figure 46 and figure 47. figure 46 . snr/sfdr vs. common - mode voltage (v cm ), f in = 9.7 mhz, f sample = 125 msps , v ref = 1.0 v figure 47 . snr/sfdr vs. common - mode voltage (v cm ), f in = 9.7 mhz, f sample = 125 msps , v ref = 1.4 v s s h c p a r c s a m p l e c s a m p l e c p a r v i n x ? h s s h v i n x+ h 1 1868-051 20 30 40 50 60 70 80 90 100 1 10 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 snr/sfdr (dbfs/dbc) v cm (v) snr (dbfs) sfdr (dbc) 1 1868-005 20 30 40 50 60 70 80 90 100 1 10 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 snr/sfdr (dbfs/dbc) v cm (v) sfdr (dbc) snr (dbfs) 1 1868-0 1 1 rev. 0 | page 21 of 44 free datasheet http://
AD9656 data shee t an on - chip, common - mode voltage reference is included in the design and is available from the vcm pin. bypass t he vcm pin to ground with a 0.1 f capacitor, as described in the applications information section. maximum snr performance is achieved by setting the adc to the largest span in a differential configuration. in the case of the AD9656 , the input span is dependent on the reference voltage (see table 11) . differential input configurations there are several ways to drive the AD9656 either actively or passively. however, optimum performance is achieved by driving the analog inputs differentially. using a differential doub le balun configuration to drive the AD9656 provides excellent performance and a flexible interface to the adc for baseband applications (see figure 48) . for applications where snr is a key parameter, differential transformer coupling is the recommended input configuration (see figure 49) because the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9656 . regardless of the configuration, the value of the shunt capacitor, c, is dependent on the input frequency and may need to be reduced or removed. it is not recommended to drive the AD9656 inputs s ingle - ended. figure 48 . differential double balun input configuration for baseband applications figure 49 . differential transformer - coupled configuration for baseband applications table 11 . reference configuration summary selected mode sense voltage (v) resulting v ref (v) resulting differential span (v p - p) fixed internal reference agnd to 0.2 v 1.0 v to 1.4 v internal , spi selectable with register 0x18 , bits[7:6] 2.0 to 2.8 programmable internal reference tie sense pin to external r divider (see figure 51) 0.5 (1 + r2/r1), for example: r1 = 3. 2 k , r2 = 5. 8 k for v ref = 1. 4 v 2 v ref fixed external reference avdd 1.0 v to 1. 4 v applied to external vref pin 2.0 to 2. 8 adc r 0 . 1 f 0 . 1 f 2 v p -p v c m c *c 1 *c 1 c r 0 . 1 f 0.1f 0 . 1 f 33 ? 200 ? 33 ? 33 ? 33 ? v i n x+ v i n x ? e t 1 - 1 - i 3 c c 5 p f r *c1 is optional. 1 1868-056 2 v p -p r r *c1 *c1 is optiona l 49 . 9 0 . 1 f ad t 1 - 1 w t 1 : 1 z ra t i o v i n x ? ad c v i n x+ *c1 c v c m 33 ? 33 ? 200? 0.1f 5pf 1 1868-057 rev. 0 | page 22 of 44 free datasheet http://
data sheet AD9656 voltage reference a stable and accurate voltage reference is built into the AD9656 . vref can be configured using the internal 1.0 v reference , using an externally appl ied 1.0 v to 1.4 v reference voltage , or using an external resistor divider applied to the internal reference to produce a user - selectable reference voltage . the reference modes are describ ed in the internal reference connection section and the external reference operation section. externally bypass t he vref pin to ground with a low equivalent series resistance ( esr ) , 1.0 f capacitor in parallel with a low esr, 0.1 f ceramic capacitor. internal reference connection a comparator within the a d9656 detects the potential at the sense pin and configures the reference for one of t hree possible modes, which are summarized in table 11 . if sense is grounded, the reference amplifier switch is connected to the internal resistor divider (see figure 50 ), setting the voltage at the vref pin, v ref , to 1.0 v. if sense is connected to an external resistor divider (see figure 51 ), v ref is defined as ? ? ? ? ? ? + = r1 r2 v ref 1 5 . 0 where: 7 k? ( r1 + r2 ) 10 k? figure 50 . 1.0 v internal reference configuration figure 51 . programmable internal reference configuratio n if the internal reference of the AD9656 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. figure 52 and figure 53 show how the internal reference volta ge is affected by loading. figure 52 . v ref error (internal v ref = 1.0 v) vs. load current figure 53 . v ref error (internal v ref = 1.4 v) vs. load current v r e f se n s e 0.5 v AD9656 se l e c t l og i c 0.1 f 1.0f vi nx? vi n x+ a d c c o r e 1 1868-054 se n s e vref 0.5 v AD9656 se l e c t l og i c 0.1 f 1.0f r2 r1 vi nx? vi n x+ a d c c o r e + 1 1868-055 ?5 ?4 ?3 ?2 ?1 0 0 0.5 1.0 1.5 2.0 2.5 v ref error (%) load current (ma) internal v ref = 1.0v 1 1868-008 ?12 ?10 ?8 ?6 ?4 ?2 0 2 0 0.5 1.0 1.5 2.0 2.5 v ref error (%) load current (ma) internal v ref = 1.4v 1 1868-014 rev. 0 | page 23 of 44 free datasheet http://
AD9656 data shee t external reference operation the use of an external reference may be necessary to enhance the gain accuracy of the adc or to improve thermal drift charac teristics. figure 54 and figure 55 show the typical drift characteristics of the internal reference in 1.0 v mode and 1. 4 v mode, respectively . figure 54 . v ref error vs. temperature, typical v ref = 1.0 v drift figure 55 . v ref error vs. temperature, typical v ref = 1.4 v drift when the sense pin is tied to avdd, the internal reference is disabled, allowing the use of an external reference. an internal reference buffer loads the external reference with an equivalent 7.5 k? load. the internal buffer generates the positive and negative full - scale references for the adc core. it is not recommended to leave the sense pin floating. clock input consider ations for optimum performance, clock the AD9656 sample clock inputs, clk+ and clk?, with a differential signal. the signal is typically ac - coupled into the clk+ and clk? pins via a transformer or capacitors. these pins are biased internally and require no external bias. clock input options th e AD9656 has a flexible clock input structure. the clock in put can be a cmos, lvds, lvpecl, or sine wave signal. regardless of the type of signal used, clock source jitter is of the most concern, as described in the jitter considerations section. figure 56 and figure 57 show two preferred methods for clocking the AD9656 (at clock rates up to 1 ghz prior to internal clock divider). a low jitter clock source is converted from a single - ended signal to a differential signal using either an rf transformer or an rf balun. the rf balun configuration is recommended for clock frequencies between 125 mhz and 1 ghz, and the rf transformer configuration is recommended for clock frequencies from 4 0 mhz to 200 mhz. the schottky diodes , across the transformer/balun secondary winding limit clock excursions into the AD9656 to approximately 0.8 v p - p differential (see figure 56 and figure 57 ) . this limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9656 while preserving the fast rise and fall times of the signal that are critical to achieving low jitter performance. however, the diode capacitance has an effect on f requencies above 500 mhz. care must be taken in choosing the appropriate sig nal limiting diode. figure 56 . transformer - coupled differential clock (up to 200 mhz) figure 57 . balun - coupled differential clock (up to 1 ghz) ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 ?40 ?15 10 35 60 85 v ref error (mv) temper a ture (c) internal v ref = 1.0v 1 1868-007 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 ?40 ?15 10 35 60 85 v ref error (mv) temper a ture (c) internal vref = 1.4v 1 1868-013 0.1f 0.1f 0.1f 0.1f schottky diodes: hsms2822 clock input 50? 100? clk? clk+ adc mini-circuits ? adt1-1wt, 1:1 z xfmr 1 1868-062 0.1f 0.1f 0.1f clock input 0.1f 50? clk? clk+ schottky diodes: hsms2822 adc 1 1868-063 rev. 0 | page 24 of 44 free datasheet http://
data sheet AD9656 if a low jitter clock source is not ava ilable, another option is to ac - cou ple a differential pecl signal to the sample clock input pins, as shown in figure 58 . the ad9510/ ad9511 / ad9512 / ad9513 / ad9514 / ad9515 / ad9516 / ad9517 clock drivers offer excellent jitter performance. figure 58 . differential pecl sample clock (up to 1 ghz) another option is to ac - couple a differential lvds signal to the sample clock input pins, as shown in figure 59 . the ad9510 / ad9511 / ad9512 / ad9513 / ad9514 / ad9515 / ad9516 / ad9517 clock drivers offer excellent jitter performance. figure 59 . differential lvds sample clock (up to 1 ghz) in some applications, it is acceptable to drive the sample clock inputs with a single - ended 1.8 v cmos signal. in such applica tions, drive the clk+ pin directly from a cmos gate, and bypass the clk? pin to ground with a 0.1 f capacitor (see figure 60 ). figure 60 . single - ended 1.8 v cmos input clock (up to 200 mhz) input clock divider the AD9656 contains an input clock divider with the ability to divide the input clock by integer values from 1 to 8. the AD9656 clock divider can be synchronized using the external sync input. bit 0 a nd bit 1 of register 0x109 allow the clock divider to be resynchronized on every sync signal or only on the first sync signal after the register is written. a valid sync causes the clock divider to reset to its initial state. this synchronization feature a llows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling . clock duty cycle typical high speed adcs use both clock edges to generate a variety of internal timing signals and, as a result, can be sensitive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the AD9656 contains a duty cycle stabilizer (dcs) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. this feature minimizes performance degradation in cases where the clock input duty cycle deviates more than the specified 5% from the nominal 50% duty cycle . ena bling the dcs function can significantly improve n oise and distortion perform ance for clock input duty cycles ranging from 30% to 45% and from 55 % to 70%. jitter in the rising edge of the input is still of concern and is not easily reduced by the internal stabilization circuit. the loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamical ly. a wait time of 1.5 s to 5 s is required after a dynamic clock frequency increase or decrease before the dcs loop is relocked to the input signal. 10 0? 0.1f 0.1f 0.1f 0.1f 240? 240? 50k? 50k? clk? clk+ clock input clock input adc ad951x pecl driver 1 1868-064 10 0? 0.1f 0.1f 0.1f 0.1f 50k? 50k? clk? clk+ adc clock input clock input ad951x lvds driver 1 1868-065 optional 100? 0.1f 0.1f 0.1f 50? 1 1 50? resistor is optional. clk? clk+ adc v cc 1k? 1k? clock input ad951x cmos driver 1 1868-066 rev. 0 | page 25 of 44 free datasheet http://
AD9656 data shee t jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency ( f a ) due only to aperture jitter ( t j ) can be calculated by snr degradation = 20 log 10 ? ? ? ? ? ? ? ? j a t f 2 1 in this equation, the rms aperture jitter represents the root sum square of all jitter sources, including the clock input, analog input signal, and adc aperture jitter specifications. if undersampling applications are particularly sensitive to jitter (see figure 61). t reat t he clock input as an analog signal in cases where aperture jitter can affect the dynamic range of the AD9656 . separate p ower supplies for clock drivers from the supplies for the adc output driver to avoid modulating the clock signal with digital noise. low jitter, crystal - controlled oscillators make the best clock sources. if the clock is generated from another type of sour ce (by gating, dividing, or other methods), retime it by the original clock at the last step. refer to the an - 501 application note and the an - 756 application note for more in - depth information about jitter performance as it relates to adcs. figure 61 . ideal snr vs. analog input frequency and jitter power dissipation an d power - down mode as shown in figure 62 and figure 63 , the power dissipated by the AD9656 is proportional to its sample rate. the AD9656 is placed in power - down mode either by the spi port or by asserting the pdwn pin high. in power - down mode , the adc typically d issipates 14 mw. during power - down, the output drivers are placed in a high impedance state. when the pdwn pin is asserted low, the AD9656 returns to normal operating mode. note that pdwn is refer enced to the digital output driver supply (drvdd) and must not exceed that supply voltage. low power dissipation in power - down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. internal capacitors are discharge d when entering power - down mode and must then be recharged when returning to normal operation. as a result, wake - up time is related to the time spent in power - down mode ; shorter power - down cycles result in proportionally shorter wake - up times. when using the spi port interface, the user can place the adc in power - down mode or standby mode. standby mode allows the user to keep the internal reference circuitry powered when faster wake - up times are required. see the memor y map section for more information about using these features. figure 62 . total power vs. f sample for f in = 9.7 mhz , four channels (v ref = 1.4 v ) figure 63 . total power vs. f sample for f in = 9.7 mhz, four channels ( v ref = 1.0 v) 1 10 100 1000 16 b i t s 14 b i t s 12 b i t s 30 40 50 60 70 80 90 100 1 10 120 130 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps a n a l og i npu t f reque n cy (m h z) 10 bits 8 bits rms clock jitter requirement snr (db) 1 1868-068 0.30 0.40 0.45 0.35 0.50 0.55 0.60 0.65 0.70 0.75 0.80 40 60 80 100 120 t ot al power (w) sample r a te (msps) 1 1868-006 80msps setting 65msps setting 50msps setting 125msps setting 105msps setting 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 40 60 80 100 120 t ot al power (w) sample r a te (msps) 125msps setting 80msps setting 65msps setting 50msps setting 105msps setting 1 1868-012 rev. 0 | page 26 of 44 free datasheet http://
data sheet AD9656 digital outputs jesd204b transmit top level description the AD9656 digital output uses the jedec standard no. jesd204b, serial interface for data converters . jesd204b is a protocol to link the AD9656 to a digital processing device over a serial interface with link speeds up to 6.4 gbps. the benefits of the jesd204b interface include a reduction in the required board area for data interface routing and the enabling of smaller packages for converter and logic devices. the AD9656 supports single , dua l, and four lane interfaces. jesd204b overview the jesd204b data transmit block , jtx, assembles the parallel data from the adc into frames and uses 8b/10b encoding , as well as optional scrambling , to form serial output data. lane synchronization is supported using special characters during the initial establishment of the link, and additional synchroniza tion is embedded in the data stream thereafter. a matching external receiver is required to lock onto the serial data stream and recover the data and clock . for additional information about the jesd204b interface, refer to the jesd204b standard. the AD9656 jesd204b transmit block maps the output of the four adcs over a link. a link can be configured to use either single , dual , or four serial differential outputs , which are called lanes. the jesd204 b specification refers to a number of parameters to define the link, and these parameters must match between the jesd204b transmitter ( AD9656 output) and receiver. the jesd204b link is described according to the following parameters: ? s = samples transmitted/single converter/frame cycle ( AD9656 value = 1) ? m = number of converters/converter device ( AD9656 value = 4 ) ? l = number of lanes/converter device ( AD9656 value = 1 , 2 , or 4 ) ? n = converter resolution ( AD9656 value = 1 6 ) ? n = total number of bits per sample ( AD9656 value = 16) ? cf = number of control words/frame clock cycle/converter device ( a d9656 value = 0) ? cs = number of control bits/conversion sample ( AD9656 value = 0 ) ? k = number of frames per multiframe (configurable on the AD9656 ) ? hd = high density mode ( AD9656 value = 0) ? f = octets/frame ( AD9656 value = 2 , 4 , or 8 , dependent upon l = 4, 2 , or 1) ? c = control bit (overrange, overflow, underflow; un available i n the AD9656 default mode ) ? t = tail bit ( un available in the AD9656 default mod e ) ? scr = scrambler enable/disable (configurable on the AD9656 ) ? fchk = checksum for the jesd204b parameters (automatically calculated and stored in the register map) figure 64 shows a simplified block diagram of the AD9656 jesd204b link. by default, the AD9656 is configured to use four converters and one lane. the AD9656 allows for other configurations such as combining the outputs of two o f the four converters onto a single lane resulting in the data from the four converters being output on two lanes. t he mapping of the 0 , 1 , 2 , and 3 digital output paths can be changed . these modes are set up through a quick configuration register in the spi register map, along with additional customizable options. by default in the AD9656 , the 1 6 - bit word from each converter is divided into two octets (8 bits of data each ). bit 0 (msb) through b it 7 are in the first octet , and bit 8 through bit 1 5 (lsb) are t he second octet . the two resulting octets can be scrambled. scrambling is optional; however, it is available to avoid spectral peaks when transmitting similar digital data patterns. the scram bler uses a self synchronizing, polynomial - based algorithm defined by the equation 1 + x 14 + x 15 . the descrambler in the receiver must be a self synchronizing version of the scrambler polynomial. the two octets are then encoded with an 8b/10b encoder. the 8b/10b encoder works by taking eight bits of data (an octet) and encoding them into a 10 - bit symbol. figure 65 shows how the 1 6 - bit data is output from the adc, the two octets are scrambled, an d how the octets are encoded into two 10 - bit symbols. figure 65 illustrates the default data format. at the data link layer, in addition to the 8b/10b encoding, character replacement is used to allow the receiver to monitor fr ame alignment. the character repl acement process occurs on the frame and multiframe boundaries, and implementation depends on which boundary is occurring and if scrambling is enabled. if scrambling is disabled, the following applies. if the last scrambled octet of the last frame of the m ultiframe equals the last octet of the previous frame, the transmitter replaces the last octet with the control character /a/ = /k28.3/. on other frames within the multiframe, if the last octet in the frame equals the last octet of the previous frame, the transmitter replaces the last octet with the control character /f/= /k28.7/. if scrambling is enabled, the following applies. if the last octet of the last frame of the multiframe equals 0x7c, the transmitter replaces the last octet with the control charac ter /a/ = /k28.3/. on other frames within the multiframe, if the last octet equals 0xfc, the transmitter replaces the last octet with the control character /f/ = /k28.7/. refer to jedec standard no. jesd 204b ( july 2011 ) for additional information about the jesd204b interface. section 5.1 covers the transport layer and data format details , and section 5.2 covers scrambling and descrambling. rev. 0 | page 27 of 44 free datasheet http://
AD9656 data shee t jesd204b synchronization details the AD9656 is a jesd204b subclass 1 device and establishes synchronization of the link through two control signals ( d sysref and d sync ) . at the system level, multiple converter devices are aligned using a common dsysref and device clock (clk). the synchronization pr ocess is accomplished over three phases: code group synchronization (cgs), initial lane alignment sequence (ilas), and data transmission. if scrambling is enabled, the bits are not actually scrambled until the data transmission phase, and the cgs phase and ilas phase do not use scrambling. cgs phase in the cgs phase, the jesd204b transmit block transmits /k28.5/ characters. the receiver (external logic device) must find k28.5 characters in its input data stream using clock and data recovery (cdr) techniques. when a certain number of consecutive k28.5 characters are detected on the link lanes, the receiver initiates a d sysref edge so that the AD9656 transmit data establishes a local multiframe clock (lmfc) internally. the dsysref edge also resets any sampling edges within the adc to align sampling instances to the lmfc. this is important to maintain synchronizati on across multiple devices. the receiver or logic device deasserts the sync~ signal applied to d sync , and the transmitter block begins the ilas phase. ilas phase in the ilas phase, the transmitter sends out a known pattern, and the receiver aligns all la nes of the link and verifies the parameters of the link. the ilas phase begins after sync~ has been deasserted (goes high). the transmit block begins to transmit four multiframes. dummy samples are inserted between the required characters so that full mul tiframes are transmitted. the four multiframes include the following: ? multiframe 1: begins with an /r/ character [k28.0] and ends with an /a/ character [k28.3]. ? multiframe 2: begins with an /r/ character followed by a /q/ [k28.4] character, followed by lin k configuration parameters over 14 configuration octets (see table 12 ), and ends with an /a/ character. ? multiframe 3: same as multiframe 1. ? multiframe 4: same as multiframe 1. table 12. 14 configuration octets of the ilas phase no. bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) 0 did[7:0] 1 bid[3:0] 2 lid[4:0] 3 scr l[4:0] 4 f[7:0] 5 k[4:0] 6 m[7:0] 7 cs[1:0] n[4:0] 8 subclass[2:0] n[4:0] 9 jesdv[2:0] s[4:0] 10 cf[4:0] 11 reserved, dont care (res1) 12 reserved, dont care (res2) 13 fchk[7:0] data transmission phase in the data transmission phase, frame alignment is monitored with control characters. character replacement is used at the end of frames. character replacement in the transmitter occurs in the following instances: ? if scrambling is disabled and the last octet of the frame or multiframe equals the octet value of the previous frame. ? if scrambling is enabled and the last o ctet of the multiframe is equal to 0x7c, or the last octet of a frame is equal to 0xfc. link setup parameters the following demonstrates how to configure the AD9656 jesd204b interface. the steps t o configure the output include the following: 1. disable the lanes before changing configuration . 2. select one quick configuration option . 3. configure the detailed options . 4. check fchk, checksum of jesd204b interface parameters . 5. set additional digital output configuration options . 6. reenable the lane(s) . disable lanes before changing configuration before modifying the jesd204b link parameters, disable the link and hold it in reset. this is accomplished by writing logic 1 to register 0x5f, bit 0. select quick configuration option write to register 0x5e, the jesd 204b quick configuration register to select the configuration options. see table 15 for the confi guration options and resulting jesd204b parameter values. ? 0x 4 1 = four converter s , one lane ? 0x 4 2 = four converter s , two lanes ? 0x 44 = four converters, four lane s ? 0x 21 = two converter s, one lane ? 0x 22 = two converter s, two lane s ? 0x 11 = one converter, one lane rev. 0 | page 28 of 44 free datasheet http://
data sheet AD9656 configure detailed options configure the tail bits and control bits. ? with n = 16 and n = 1 4 (nondefault configuration) , two bits are available per sample for transmitting additional information over the jesd204b link. the options are tail bits or c ontrol bits. by default, tail bits of 0b00 value are used. ? tail bits are dummy bits sent over the link to complete the two octets and do not convey any information about the input signal. tail bits can be fixed zeros (default) or pseudo - random numbers (register 0x5f, bit 6). ? one or two control bits can be selected to replace the tail bits using register 0x72, bits[7:6]. the meaning of the control bits can be set using register 0x14, bits[7:5]. set lane identification values. ? jesd204b allows parameters to identify the device and lane. these parameters are transmitted during the ilas phase, and they are accessible in the internal registers. ? the three identification values are device identification (did), bank identification (bid), and lane identification (lid). did and bid are device specific; therefore, they can be used for link identification. set the number of frames per multiframe, k . ? per the jesd204b specification, a multiframe is defined as a group of k successive frames, where k is from 1 t0 32, and requires that the number of octets be from 17 to 1024. the k value is set to 32 by default in register 0x70, bits[ 4 :0 ] . note that the k value is the register value plus 1. ? the k value can be changed; however, it must comply with a few conditions. the AD9656 uses a fixed value for octets per frame [f] based on the jesd204b quick configuration setting. k must also be a multiple of 4 and conform to the following equation : 32 k ceil (17/ f ) ? the jesd204b specification also specifies that the number of octets per multiframe (k f) be from 17 to 1024. the f value is fixed through the quick configuration setting to ensure that this relationship is true. table 13 . jesd 204b configurable identification values did value register, bits value range lid (lane 0) 0x6 6 , [4:0] 031 lid (lane 1) 0x6 7 , [4:0] 031 did 0x64, [7:0] 0255 bid 0x65, [3:0] 015 scramble, scr. ? scrambling can be enabled or disabled by setting register 0x6e, bit 7. by default, scrambling is enabled. per the jesd204b protocol, scrambling is functional only after the lane synchronization has completed. select lane synchronization options. most of the synchronization features of the jesd204b inter face are enabled by default for typical applications. in some cases, these features can be disabled or modified as follows: ? ilas enabling is controlled in register 0x5f, bits[3:2] and is enabled by default. optionally, to support some unique instances of t he interfaces (such as nmcda - sl), the jesd204b interface can be programmed to either disable the ilas sequence or continually repeat the ilas sequence . the AD9656 has fixed values f or some jesd20 4b interface parameters, and they are as follows: ? [n] = 16: number of bits per sample is 16, in register 0x73, bits[4:0] ? [cf] = 0: number of control words/frame clock cycle/converter is 0, in register 0x75, bits[4:0] verify read only values: lanes per li nk (l), octets per frame (f), number of converters (m), and samples per converter per frame (s). the AD9656 calculates values for some jesd204b parameters based on other settings, particularly the quick configuration register selection. the following read only values are available in the register map for verification. ? [l] = lanes per link can be 1 , 2 or 4 ; read the values from register 0x6e, bits [4:0] ? [f] = octets per frame can be 2 , 4 , or 8 ; read the value from register 0x6f, bits[7:0] ? [hd] = high density mode is 0 ; read the value from register 0x75, bit 7 ? [m] = number of converters per link ; default is 4 , but can be 1, 2 , or 4. r ead the value from register 0x71, bits[7:0] ? [s] = samples per converter per frame is 1 ; read the value from register 0x74, bits[4:0] rev. 0 | page 29 of 44 free datasheet http://
AD9656 data shee t check fchk, checksum of jesd204b interface parameters the jesd204b parameters can be verified through the checksum value [fchk] of the jesd204b interface parameters. each lane has a fchk value associated with it. the fchk value is transmitted during the ilas second multiframe and can be read from the internal registers. the checksum value is the modulo 256 sum of the p arameters listed in the no. column of table 14 . the checksum is calculated by adding the parameter fields before they are packed into the octets shown in table 14 . the fchk for the lane configuration for data exiting lane 0 can be read from register 0x7 8 . similarly, the fchk for the lane configuration for data exiting lane 1 can be read from register 0x7 9 , fchk for lane 2 can be read from register 0x7a , and fchk for lane 3 can be read from register 0x7b. table 14. jesd204b configuration table used in ilas and chksum calculation no. bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) 0 did[7:0] 1 bid[3:0] 2 lid[4:0] 3 scr l[4:0] 4 f[7:0] 5 k[4:0] 6 m[7:0] 7 cs[1:0] n[4:0] 8 subclass[2:0] n[4:0] 9 jesdv[2:0] s[4:0] 10 cf[4:0] set additional digital output configuration options other data format controls include the following: ? invert polarity of serial output data: register 0x60, bit 1 ? adc data format (offset binary or twos complement): register 0x14, bits[1:0] ? options for interpreting si gnal on d sysref and d sync: register 0x3a , bits[4:3] ? option to remap converter (logical lane) and serdoutx (physical lane ) assignments : register 0x82 and register 0x83. see figure 64 for a simplified block diagram. re e nable lanes after configuration after modifying the jesd204b link parameters, enable the link so that the synchroniza tion process can begin. this is accomplished by writing logic 0 to register 0x5f, bit 0. figure 64 . AD9656 transmit link simplified block diagram 1 1868-069 converter a converter b converter c converter d crosspoint switch serdout0 serdout1 serdout2 serdout3 see register 0xf5 description jesd204b lane contro l (m = 4, l = 1, 2, 4) lane mux vina+/ vina? vinb+/ vinb? vinc+/ vinc? vind+/ vind? dsync+/ dsync? dsysref+/ dsysref? rev. 0 | page 30 of 44 free datasheet http://
data sheet AD9656 figure 65 . AD9656 digital processing of jesd204b lanes table 15. AD9656 jesd204b typical configurations jesd 204 b quick configuration setting, register 0x5e m (no. of converters), register 0 x 71 , bits[7:0] l (no. of lanes), register 0 x 6 e, bits[ 4:0] f (octets/frame), register 0 x 6 f, bits[7:0], read only s (samples/adc/frame), register 0 x 74 , bits[ 4:0 ], read only hd (high density mode), register 0 x 75 , bit[ 7 ], read only 0x 4 1 4 1 8 1 0 0x 4 2 4 2 4 1 0 0x 44 4 4 2 1 0 0x 22 2 2 2 1 0 0x 21 2 1 4 1 0 0x 11 1 1 2 1 0 figure 66 . AD9656 adc output data path table 16. AD9656 jesd204b frame alignment monitoring and correction replacement characters scrambling lane synchronization character to be replaced last octet in multiframe replacement character off on last octet in frame repeated from previous frame no k28.7 off on last octet in frame repeated from previous frame yes k28.3 off off last octet in frame repeated from previous frame not applicable k28.7 on on last octet in frame equals d28.7 no k28.7 on on last octet in frame equals d28.3 yes k28.3 on off last octet in frame equals d28.7 not applicable k28.7 frame and lane alignment monitoring and correction frame alignment monitoring and correction is part of the jesd204b specification . the 1 6 - bit word requires two octets to transmit all the data. the two octets (msb and lsb), where f = 2, make up a frame. during normal operating conditions, frame alignment is monitored via alignment characters, which are inserted under certain conditions at th e end of a frame. table 16 summarizes the conditions for character insertion , along with the expected characters under the various operation modes. if lane synchronization is enabled, the replacement character value depends on whether the octet is at the end of a frame or at the end of a multiframe. based on the operating mode, the receiver can ensure that it is still synchronized to the frame boundary by correctly receiving the replacement characters. 8b/10b encoder/ character replacment serializer t . . . dsync dsysref vina+ vina? serdout a path adc test pattern 16-bit jesd204b test pattern 8-bit adc a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a0 octet0 octet1 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 e0 e1 e2 e3 e4 e5 e6 e7 e10 e11 e12 e13 e14 e15 e16 e17 e8 e9 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 e18 e19 e19 optional scrambler 1 + x 14 + x 15 jesd204b test pattern 10-bit 1 1868-070 data from adc frame assembler (add tail bits) optional scrambler 1 + x 14 + x 15 8b/10b encoder to receiver 1 1868-071 rev. 0 | page 31 of 44 free datasheet http://
AD9656 data shee t digital outputs and timing the AD9656 has differential digital outputs that power up by default. t he driver current is derived on chip and sets the output current at each output equal to a nominal 4 ma. each output presents a 100 ? dynamic internal termination to reduce unwanted reflections. place a 100 ? differential termination resistor at each receiver input to result in a nominal 6 00 mv p - p differential swing at the receiver (see figure 67 ). alternatively, single - ended 50 ? termination can be used. when single - ended termination is used, th e termination voltage must be drvdd/2; otherwise, ac coupling capacitors can be used to terminate to any single - ended voltage. figure 67 . ac - coupled digital output termination example the AD9656 digital outputs can interface with custom asics and fpga receivers, providing superior switching performance in noisy environments. single point - to - point network topologies are recommended with a single differential 100 ? termination resistor placed as close to the receiver logic as possible. the common mode of the digital output automatically biases itself to half the supply of the receiver (that is, the common - mode voltage is 0.9 v for a receiver supply of 1.8 v) if a dc - coupled connecti o n is used (see figure 68 ). for receiver logic that is not within the bounds of the drvdd supply, use an ac - coupled connection. p lace a 0.1 f capacitor on each output pin and derive a 100 ? differential termination close to the receiver side. figure 68 . dc - coupled digital output termination example if there is no far - end receiver termination, or if there is p oor differential trace routing, timing errors can result. to avoid such timing errors, it is recommended that the trace length be less than six inches, and that the differential output traces be close together and of equal lengths. figure 69 shows an example of the digital output data eye and time interval error (tie) jitter histogram and bathtub curve for the AD9656 lane running at 6.4 gbps. additional spi options allow the user to further increase the output driver voltage swing of all four outputs to drive longer trace lengths (see register 0x15 in table 19 ). the power dissipation of the drvdd supply increases when this option is used. see the memory map section for more information . the format of the output data is twos complement by default. to change the output data format to offset binary, see the memory map section and register 0x14 in table 19. figure 69. AD9656 digital outputs data eye, histogram , and bathtub, ext ernal 100 ? terminations at 6.4 gbps 100? 100? differential trace pair serdoutx+ drvdd v rxcm serdoutx? v cm = rx v cm output swing = 600mv p-p differential 0.1f 0.1f receiver 1 1868-072 100? 100? differentia l trace p air d r vdd v cm = d r vdd/2 output swing = 600mv p-p differentia l receiver serdoutx+ serdoutx? 1 1868-073 0 ? 0 . 5 0 . 5 uis pe r i o d 1 : h i s t o g r a m 350 400 450 ?10 ?5 5 0 time (ps) 10 300 250 200 50 0 100 150 1 ?16 1 ?14 1 ?12 1 ?10 1 ?8 1 ?6 1 ?4 1 ?2 1 ber 3 2 ? ?100 ?50 50 ?150 150 0 100 t i me (p s ) 400 300 200 100 0 ?100 ?300 ?400 ?200 voltage (mv) h e i g h t 1 : eye d i a g r a m 1 ? tj@ber1: b athtub hits ey e: all bits offset: ?0.0108 uls: 6000; 57327 total: 6000.57327 0.81 ui 1 1868-074 rev. 0 | page 32 of 44 free datasheet http://
data sheet AD9656 serial port interfac e (spi) the AD9656 serial port interface (spi) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the adc. the spi gives the user added flexibility and customization, depending on the applicati on. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided into fields. these fields are documented in the memory map section. for general operational information, see the an - 877 application note , interfacing to high speed adcs via spi . configuration using the spi three pins define the spi of this adc: the sclk pin, the sdio pin, and the csb pin (see table 17 ). the sclk (serial clock) pin is used t o synchronize the read and write data presented from/to the adc. the sdio (serial data input/output) pin is a dual purpose pin that allows data to be sent and read from the internal adc memory map registers. the csb (chip select bar) pin is an active low c ontrol that enables or disables the read and write cycles. table 17 . serial port interface pins pin function sclk serial clock. the serial shift clock input, which is used to synchronize serial interface reads and writes. sdio serial data input/output. a dual purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. csb chip select bar. an active low control that gates the read and write c ycles. the falling edge of csb , in conjunction with the rising edge of sclk, determines the start of the framing. an example of the serial timing and its definitions can be found in figure 70 and table 7 . other modes involving the csb pin are available. the csb pin can be held low indefinitely, which permanently e nables the device; this is called streaming. the csb pin can stall high between bytes to allow for additional external timing. when csb is tied high, spi functions are placed in a high impedance mode. this mode turns on any spi pin secondary functions. during an instruction phase, a 16 - bit instruction is transmitted. data follows the instruction phase, and its length is determined by the w0 and the w1 bits. all data is composed of 8 - bit words. the first bit of each individual byte of serial data indicate s whether a read or write command is issued. this allows the sdio pin to change direction from an input to an output. in addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial po rt to be used both to program the chip and to read the contents of the on - chip memory. if the instruction is a readback operation, performing a readback causes the sdio pin to change direction from an input to an output at the appropriate point in the seri al frame. input data is registed on the rising edge of sclk, and output data is transmited on the falling edge. after the address information passes to the converter that is requesting a read, the sdio line transitions from an input to an output within on e - half of a clock cycle. this timing ensures that when the falling edge of the next clock cycle occurs, data can be safely placed on this serial line for the controller to read. data can be sent in msb first mode or in lsb first mode. msb first is the defa ult on power - up and can be changed via the spi port configuration register. for more information about this and other features, see the an - 877 application note , interfacing to high speed adcs via spi . hardware interface the pins described in table 17 make up the physical interface between the user programming device and the serial port of the AD9656 . the sclk pin and the csb pin function as inputs when using the spi interface. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. the spi interface is flexible enough to be controlled by either fpgas or microcontrollers. one method for spi configuration is described in detail in the an - 812 application note , microcontroller - based serial port interface (spi) boot circuit . w hen the full dynamic performance of the conve rter is required , do not activate t he spi port. because the sclk signal, the csb signal, and the sdio signal are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9656 to prevent these signals from transitioning at the converter inputs during critical sampling periods. rev. 0 | page 33 of 44 free datasheet http://
AD9656 data shee t spi access ible features table 18 provides a brief description of the features that are accessible via the spi. these features are described in general in the an - 877 application note , interfacing to high speed adcs via spi . the AD9656 part - specific features are described in the memory map register descriptions section. information in the AD9656 data sheet takes precedence over information in an - 877 application note , where it relates to the AD9656 . table 18 . features accessible using the spi feature name description mode allows the user to set either power - down mode or standby mode clock allows the user to access the duty cycle stabilizer via the spi offset allows the user to digitally adjust the converter offset test input/output allows the user to set test modes to place known data on the output bits output mode allows the user to set up the outputs vref allows the user to set the reference voltage figure 70 . serial port interface timing diagram d o n ? t car e d o n ? t car e d o n ? t car e d o n ? t car e s d i o s c l k t s t d h t c l k t d s t h r / w w 1 w 0 a1 2 a1 1 a1 0 a 9 a 8 a 7 d 5 d 4 d 3 d 2 d 1 d 0 t l o w t h ig h 1 1868-075 csb rev. 0 | page 34 of 44 free datasheet http://
data sheet AD9656 memory map reading the memory m ap register table each row in the memory map register table has eight bit locations . the memory map is roughly divided into three sections: the chip configuration registers (address 0x00 to address 0x02); the channel index and transfer registers (address 0 x 05 and address 0xff); and the adc functions registers, including setup, control, and test (address 0x08 to address 0x 10a ) . the memory map register table ( s e e table 19 ) documents the default hexadecimal value for each hexadecimal address shown. the column with the heading bit 7 (msb) is the start of the default hexadecimal value given. for example, address 0x14, the output mode regi ster, has a hexadecimal default value of 0x0 1 . this means that bit 0 = 1 and the remaining bits are 0s. this setting is the default output format value, which is twos complement. for general information on this function and others, see the an - 877 application note , interfacing to high speed adcs via spi . see table 19 for spi register information specific to the AD9656 . open and reserved locations all address and bit locations that are not included in table 19 are not supported for this device. write 0s to u nused bits of a valid address location. wri ting to these locations is required only when part of an address location is open (for example, address 0x18). if the entire address location is open (for example, address 0x13), do not write to this address location. default values after the AD9656 is reset, critical registers are loaded with default values. the default values for the registers are given in the memory map register table (see table 19) . logic levels an explanation of logic level terminology follows: ? bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. ? clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. channel - specific registers some ch annel setup functions can be programmed to a different value for each channel. in these cases, channel address locations are internally duplicated for each channel. these registers and bits are designated in table 19 as local. these local registers and bits can be accessed by s etting the appropriate channel 0 , channel 1 , channel 2 , or channel 3 bit in register 0x05. if four bits are set, the subsequent write affects the registers of all four channels . in a read cycle, set only one of the channels to read one of the four registers. if all bits are set during an spi read cycle, the device returns the value for channel 0 . registers and bits designated as global in table 19 affect the entire device and the channel features for which independent settings are not allowed between channels. the settings in register 0x05 do not affect the global reg isters and bits. rev. 0 | page 35 of 44 free datasheet http://
AD9656 data shee t memory map register table the AD9656 uses a 3 - wire interface and 16 - bit addressing . bit 0 and bit 7 in register 0x00 are set to 0, and bit 3 and bit 4 are set to 1. when bit 5 in register 0x00 is set high, the spi enters a soft reset, where all of the user registers revert to their default v alues and bit 2 is automatically cleared. table 19 . memory map registers ( spi registers /bits not labeled local are global ) addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) notes/ comments chip configuration registers 0x00 spi port configuration 0 lsb first soft reset 1 1 soft reset lsb first 0 0x18 0x01 chip id 8 - bit chip id[7:0]; AD9656 = 0x c0 (quad , 16 - bit , 125 msps , jesd204b) 0x c0 read only. 0x02 chip grade open speed grade id[6:4]; 110 = 125 msps open open open open 0x60 read only. channel index and transfer registers 0x05 device index open open open open data channel 3 data channel 2 data channel 1 data channel 0 0x0 f 0xff transfer open open open open open open open initiate r eg ister 0x100 override ( self - clear ing) 0x00 adc functions 0x08 power modes open open p d wn pin function: 0 = full power - down, 1 = standby jtx standby mode : 0 = ignore standby, 1 = do not ignore standby reserved p ower mode : 00 = normal operation, 01 = full power - down, 10 = standby, 11 = digital reset 0x00 0x09 c lock open 0 open open open open open duty cycle stabilizer: 0 = off, 1 = o n 0x0 0 0x 0a pll_status pll locked status bit: 0 = pll is not locked, 1 = pll is locked open open open open open open jtx link status: 0 = not ready, 1 = ready read only . 0x0b clock divider open open open open open clock divider ratio[2:0]: 000 = divide by 1, 001 = divide by 2, 010 = divide by 3, 011 = divide by 4, 100 = divide by 5, 101 = divide by 6, 110 = divide by 7, 111 = divide by 8 0x00 0x0c enhancement control open open open open open chop mode: 0 = off, 1 = on open open 0x00 0x0d test mode (local except for pseudo - random n umber (pn) sequence resets) user input test mode: 00 = single, 01 = alternate, 10 = single once, 11 = alternate once, (affects user input test mode only, bits[3:0] = 1000) reset pn long gen erator reset pn short generator output test mode[3:0] (local): 0000 = off (default), 0001 = midscale short, 0010 = positive full scale (fs), 0011 = negative fs, 0100 = alternating checkerboard, 0101 = pn23 sequence, 0110 = pn9 sequence, 0111 = one/zero word toggle, 1000 = user input, 1001 = 1/0 bit toggle, 1010 = 1 sync, 1011 = one bit high, 1100 = mixed bit frequency 0x00 when set, the test data is placed on the output pins in place of norm al data. 0x10 offset adjust (local) 8 - bit device offset adjustment [7:0] (local); offset adjusts in lsbs from +127 to ?128 (twos complement format) 0x00 device offset trim. rev. 0 | page 36 of 44 free datasheet http://
data sheet AD9656 addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) notes/ comments 0x14 output mode jtx cs mode : 000 = {overrange||underrange, valid flag }, 001 = {overrange, underrange}, 010 = {overrange||underrange, blank}, 011 = {blank, valid flag }, 100 = {blank, blank}, others = {overrange||underrange, valid flag } adc output valid flag : 0 = output valid , 1 = output invalid ( local ) open open output format: 0 = offset binary, 1 = twos complement 0x0 1 0x15 output adjust open open open open open typical cml differential output drive level: 00 0 = 473 mv p- p, 00 1 = 524 mv p- p, 010 = 574 mv p- p, 0 1 1 = 621 mv p- p (default) , 1 00 = 667 mv p- p, 101 = 716 mv p - p, 110 = 7 63 mv p - p, 111 = 811 mv p - p 0x0 3 0x16 clock phase control open input clock phase adjust[2:0] (value is number of input clock cycles of phase delay) open open open open 0x00 0x18 input span select internal vref adjustment[1:0]: 00 = 1 .0 v, 01 = 1 .2 v, 10 = 1 .3 v, 11 = 1 .4 v open open open differential span adjustment: 000 = 50% of normal , 001 = 57% of normal , 010 = 67% of normal , 011 = 80% of normal , 100 = normal 0x0 4 0x19 user test pattern 1 lsb user test pattern 1[7:0] 0x00 0x1a user test pattern 1 msb user test pattern 1[15:8] 0x00 0x1b user test pattern 2 lsb user test pattern 2[7:0] 0x00 0x1c user test pattern 2 msb user test pattern 2[15:8] 0x00 0x21 flex_serial_ control open open open open pll low rate mode : 0 = lane rate 2 gbps 1 = lane rate < 2 gbps open open open 0x00 0x22 flex_serial_ ch_stat open open open open open open open channel power - down (local) 0x00 0x3a sysref_ctrl open open open 0 = normal mode , 1 = realign the lanes on every active d sync 0 = realign the lanes only when d sysref causes a resync of the counters, 1 = realign the lanes on every d sysref open open open 0x00 0x3 b realign_ pattern_ctrl this pattern is written into the fifo when a lane is being aligned: 00 = lane outputs constant zero, 55 = lane outputs toggling pattern 0x 55 0x5e jesd204b quick configuration 0x41 = four converters, one lane ; 0x42 = four converters, two lanes ; 0x44 = four converters, four lanes ; 0x22 = two conver ters, two lanes; 0x21 = two converters, one lane; 0x11 = one converter, one lane 0x00 self clearing, always reads 0x00. rev. 0 | page 37 of 44 free datasheet http://
AD9656 data shee t addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) notes/ comments 0x5f jesd204b link ctrl 1 open tail bits mode: 0 = fill with 0s , 1 = fill with 9 - bit pn sequence jtx transport layer test: 0 = not enabled, 1 = long transport layer test enabled multiframe alignment character insertion: 0 = disabled, 1 = enabled ilas mode: 00 = ilas disabled, 01 = ilas enabled (normal mode ), 11 = ilas always on ( test mode ) frame alignment character insert ion: 0 = enabled, 1 = disabled 0 = jtx link enabled, 1 = jtx link disabled 0x14 0x60 jesd204b link ctrl 2 reserved d sync pin invert: 0 = not inverted, 1 = inverted d sync pin input bias : 0 = disabled , 1 = enabled open open jtx output invert : 0 = normal, 1 = inverted reserved 0x10 0x61 jesd204b link ctrl 3 reserved reserved test data injection point: 01 = 10 - bit data injected at 8b/10b encoder output, 10 = 8 - bit data at scrambler input j tx test mode patterns: 0000 = normal operation (test mode disabled), 0001 = alternating checkerboard, 0010 = 1/0 word toggle, 0011 = pn sequence pn23, 0100 = pn sequence pn9, 0101= continuous/repeat user test mode, 0110 = single user test mode, 0111 = reserved, 1000 = mo dified rpat test sequence ( 8 - bit data only ), 1100 = pn sequence pn7, 1101 = pn sequence pn15, other setting are unused 0x00 0x62 jesd204b link ctrl 4 reserved 0x00 0x64 jesd204b did configuration d evice identification (did) = c0 0x c 0 read only. 0x65 jesd204b bid configuration open open open open jtx bank identification (bid) number 0x00 0x6 6 jesd204b lid configuration 0 open open open jtx lane identification (lid) number for lane 0 0x00 0x67 jesd204b lid configuration 1 open open open jtx lane identification (lid) number for lane 1 0x01 0x68 jesd204b lid configuration 2 open open open jtx lane identification (lid) number for lane 2 0x02 0x6 9 jesd204b lid configuration 3 open open open jtx lane identification (lid) number for lane 3 0x03 0x6e jesd204b parameters , scr/l jesd204b scrambling (scr): 0 = disabled, 1 = enabled open open jesd204 b serial lane control : 0 = one l ane per link (l = 1), 1 = two l anes per link (l = 2), 2 = unused, 3 = four lanes per link (l = 4), 4 to 31 = unused 0x80 0x6f jesd204b parameters , f jesd204b number of octets per frame (f); calculated value, f = (2 m ) /l 0x00 read only. 0x70 jesd204b parameters , k open open open jesd204 b number of frames per multiframe (k); k = register contents + 1, but also must be a multiple of four octets 0x1f 0x71 jesd204b parameters , m jesd204b number of converters (m): 0 = one converter (m = 1) , 1 = two converters (m = 2) , 3 = four converters (m = 4, default) 0x03 0x72 jesd204b parameters , cs/n 00 = number of control bits sent per sample (cs = 0) open jtx converter resolution (n) : 0x0f = 16 - bit , 0x0d = 14 - bit, 0x0b = 12 - bit, 0x09 = 10 - bit 0x0f 0x73 jesd204b parameters , subclass/np jesd204b subclass; 0x0 = subclass 0; 0x1 = subclass 1 (default) jesd204b number of bits per sample ( n ); n = register contents + 1 0x2f 0x74 jesd204b parameters , s reserved jesd204b converter samples per frame (s); s = register contents + 1 0x20 read only. 0x75 jesd204b parameters , hd and cf jesd204b hd value = 0 open open jesd204b control words per frame clock cycle per link (cf = 0, fixed ) 0x00 read only. 0x76 jesd204b resv1 jesd204 b serial reserved field no. 1 in link config uration, see table 12 (res1) 0x00 0x77 jesd204b resv2 jesd204 b serial reserved field no. 2 in link configuration, see table 12 (res2) 0x00 0x7 8 jesd204b chksum0 jesd204 b serial checksum value in link configuration, see table 12 for lane 0 (fchk) read only. rev. 0 | page 38 of 44 free datasheet http://
data sheet AD9656 addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) notes/ comments 0x79 jesd204b chksum 1 jesd204 b serial checksum value in link configuration, see table 12 for lane 1 (fchk) read only. 0x7 a jesd204b chksum2 jesd204 b serial checksum value in link configuration, see table 12 for lane 2 (fchk) read only. 0x7b jesd204b chksum 3 jesd204 b serial checksum value in link configuration, see table 12 for lane 3 (fchk) read only. 0x 80 jtx physical lane disable open open open open lane 3 : 0 = enabled, 1 = disable d lane 2 : 0 = enabled, 1 = disable d lane 1 : 0 = enabled, 1 = disable d lane 0 : 0 = enabled, 1 = disable d 0x00 lane serialize and output driver powered down. 0x82 jesd204b lane assign 1 open physical lane 1 assignment: 000 = logical lane 0, 001 = logical lane 1, 010 = logical lane 2, 011 = logical lane 3 open physical lane 0 assignment: 000 = logical lane 0, 001 = logical lane 1, 010 = logical lane 2, 011 = logical lane 3 0x 10 0x8 3 jesd204b lane assign 2 open physical lane 3 assignment: 000 = logical lane 0, 001 = logical lane 1, 010 = logical lane 2, 011 = logical lane 3 open physical lane 2 assignment: 000 = logical lane 0, 001 = logical lane 1, 010 = logical lane 2, 011 = logical lane 3 0x 32 0x8 6 jesd204b lane inversion open open open open lane 3 : 0 = no invert, 1 = invert lane 2 : 0 = no invert, 1 = invert lane 1 : 0 = no invert, 1 = invert lane 0 : 0 = no invert, 1 = invert 0x00 0x8b jesd204b lmfc offset open open open local multiframe clock (lmfc) phase offset value; reset value for lmfc phase counter when d sysref is asserted; used for deterministic delay applications 0x00 0xa0 jtx user patter n o ctet 0 , lsb user test pattern least significant byte , octet 0 0x00 0xa1 jtx user pattern o ctet 0 , msb user test pattern most significant byte , octet 0 0x00 0xa2 jtx user pattern o ctet 1 , lsb user test pattern least significant byte , octet 1 0x00 0xa3 jtx user pattern o ctet 1 , msb user test pattern most significant byte , octet 1 0x00 0xa4 jtx user pattern o ctet 2 , lsb user test pattern least significant byte , octet 2 0x00 0xa5 jtx user pattern octet 2 , msb user test pattern most significant byte , octet 2 0x00 0xa6 jtx user pattern octet 3 , lsb user test pattern least significant byte , octet 3 0x00 0xa7 jtx user pattern octet 3 , msb user test pattern most significant byte , octet 3 0x00 0xf5 jtx converter mapping jtx converter 3: 0 = adca, 1 = adcb, 2 = adcc, 3 = adc d jtx converter 2: 0 = adca, 1 = adcb, 2 = adcc, 3 = adc d jtx converter 1: 0 = adca, 1 = adcb, 2 = adcc, 3 = adc d jtx converter 0: 0 = adca, 1 = adcb, 2 = adcc, 3 = adc d 0xe4 0x100 resolution/ sample rate override open override enable resolution: 0 = 16 bits, 1 = 14 bits, 2 = 12 bits, 3 = 10 bits open sample rate: 001 = 40 msps, 010 = 50 msps, 011 = 65 msps, 100 = 80 msps, 101 = 105 msps, 110 = 125 msps 0x00 sample rate override (requires transfer register, 0xff). 0x101 user i/o control 2 open open open open open open open sdio pull - down 0x00 disables sdio pull - down. 0x102 user i/o control 3 open open open open vcm power - down open open open 0x00 vcm control. rev. 0 | page 39 of 44 free datasheet http://
AD9656 data shee t addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) notes/ comments 0x109 clock divider sync control clock divider sync mode: 0 = use sync pin, 1 = use dsysref pins reserved reset clock divider sync received sync clock divider enable: 0 = disabled, 1 = enabled 0x00 0x10a clock divider sync received open open open open open open open clock divider sync received 0x00 read only. memory map register descriptions for additional general information about functions controlled in register 0x00 to register 0xff, see the an - 877 application note , interfacing to high speed adcs via spi . device index (register 0x05) c ertain features in the map that are designated as local can be set independently for each channel, whe reas other features apply globally to all channels (depending on context) , regardless of the channel is selected. bits[3:0] of register 0x05 can be used to select which data channels are affected. transfer (register 0xff) all registers except register 0x1 00 are updated the moment they are written. setting bit 0 of th e transfer register high initializes the settings in the resolution/ sample rate override register (address 0x100). power modes (register 0x08) bit 5 pd pin function if set to 1 , the pdwn pin initiates standby mode. if set to 0 (cleared) , the pdwn pin initiates full power - down mode. bit 4 jtx standby mode if set, the jtx block enters standby mode when chip standby is activated. o nly t he pll is left running i n standby mode. if cle ared, the jtx block remains running when chip standby is activated. bits[1:0] power mode in normal operation (bits[1:0] = 00), all adc channels and the jtx block are active. in full power - down mode (bits[1:0] = 01), all adc channels and the jtx block are powered down , and the digital datapath clocks are disabled , while the digital datapath is reset. the o utputs are disabled . in standby mode (bits[1:0] = 10), all adc channels are partially powered down , and the digital datapath clocks are disable d. if jtx standby m ode is set , the outputs are also disabled. during a digital reset (bits[1:0] = 11), all the digital datapath clocks and the outputs (where applicable) on the chip are reset, except for the spi port. note that the spi is always left under control of the user; that is, it is never automatically disabled or in reset (except by power - on reset). when the digital reset is deactivated , a foreground calibration sequence is initiated. enhancement control (register 0x0c) bit 2 chop mode for applica tions that are sensitive to offset voltages and other low frequency noise, such as homodyne or direct conversion receivers, chopping in the first stage of the AD9656 is a feature that can be enabled by setting bit 2. in the frequency domain, chopping translates offsets and other low frequency noise to f clk /2 where it can be filtered. output mode (regis ter 0x14) bit s 75 jtx cs mode defines the meaning of the jtx control bits. bit s[ 1: 0 ] output format by default, this field is set to 1 for data output in twos complement format. setting this field to 0 changes the output mode to offset binary. rev. 0 | page 40 of 44 free datasheet http://
data sheet AD9656 clock phase control (register 0x16) bits[6:4] input clock phase adjust when the clock divider (register 0x0b) is used, the applied clock is at a higher frequency than the internal sampling clock. bits[6:4] determine at which phase the external clock sampling occurs. this is only applicable when the clock divider is used. setting bits[6:4] greater than register 0x0b , bits[2:0] is prohibited. table 20 . input clock phase adjust options input clock phase adjust, bits[6:4] number of input clock cycles of phase delay 000 ( d efault) 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 jtx user pattern ( register 0x a0 to register 0x a7 ) the pattern in these registers is output on all active lanes when register 0x61 , b its[3:0] are set to 5 or 6. a 32 - bit pattern, the concatenation of register 0xa0, register 0xa2 , register 0xa4 , and register 0xa6 is inserted before the scrambler if register 0x61 , b its[5:4] are set to 2. if register 0x61 , b its[5:4] are set to 1 ( a 40 - bit pattern ) , the concatenation of register 0xa1 , b its[1:0] and register 0xa0 , b its[7:0] ; register 0xa3 , b its[1:0] and register 0xa2 , b its[7:0] ; register 0xa5 , b its[1:0] and register 0xa4 , b its[7:0] ; register 0xa7 , b its[1:0] and register 0xa6 , b its[7:0] is inserted after the 8b10b encoder. resolution/ sample rate override (register 0x100) this register allow s the user to downgrade the resolution and/or the maximum sample rate (for lower power) in applications that do not require full resolution and/or sample rate . settings in this register are not initialized until bit 0 of the transfer register (register 0xff) is written high. bits[2:0] do not affect the sample rate; they affect the maximum sample rate capability of the adc. user i/o control 2 (register 0x101) bit 0 sdio pull - down bit 0 can be set to disable the internal 30 k pull - down resistor on the sdio pin . this setting can be used to limit the loading when many devices are connected to the spi bus. user i/o control 3 (register 0x102) bit 3 vcm power - down bit 3 can be set high to power down the internal vcm generator. this feature is used when applying an external reference. rev. 0 | page 41 of 44 free datasheet http://
AD9656 data shee t applications informa tion design guidelines before starting system level design a nd layout of the AD9656 , it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and l ayout requirements needed for certain pins. power and ground rec ommendations when connecting power to the AD9656 , it is recommended that two separate 1 .8 v supplies be used: one supply for analog (avdd), a nd a separate supply for the digital outputs (drvdd and dvdd ). the designer can use several different decoupling capacitors to cover both high and low frequencies. locate t hese capacitors close to the point of entry at the printed circuit board ( pc b) level and close to the pins of the part with minimal trace length. when usin g the AD9656 , a single pcb ground plane is sufficient . with proper decoupling and smart partitioning of the pcb analog, digital, and clock sections, optimum performance is easily achieved. clock stability cons iderations when powered on, the AD9656 enters an initialization phase during which an internal state machine sets up the biases and the registers for proper operation. during the initialization process, the AD9656 needs a stable clock. if the adc clock source is not present or not stable during adc power - up, it disrupt s the state machine and cause s the adc to start up in an unknown state. to correct this, an initialization sequence must be reinvoked after the adc clock is stable. b y issuing a digital reset via register 0x08. in the default configuration (internal v ref , a c - coupled input) where v ref and v cm are supplied by the adc itself, a stable clock during power - up is sufficient. in the case where v ref and/or v cm are supplied by an external source, these , too , must be stable at power - up; otherwise, a subsequent digital reset via register 0x08 is needed. the pseudo code sequence for a digital reset is as follows: spi_write (0x08, 0x03); # digital reset spi_write (0x08, 0x00); # normal operation exposed pad thermal heat slug recommendations it is mandatory that the exposed pad on the underside of the adc be connected to analog ground (agnd) to achieve the best electrical and thermal performance. a continuous, exposed (no solder mask) copper plane on the pcb must mate to the AD9656 exposed pad, pin 0. the copper plane must have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. fill or plug t hese vias with nonconductive epoxy. to maximize the coverage and adhesion between the adc and the pcb, overlay a silkscreen to partition the continuous plane on the pcb into several uniform sections. this partitioning prevents th e solder from pooling and provides several tie points between the adc and the pcb during the reflow process. using one continuous plane with no partitions guarantees only one tie point between the adc and the pcb. see the evaluation board for a pcb layout example. for detailed information about the packaging and pcb layout of chip scale packages, refer to the an - 772 application note , a design and manufacturing guide for the lead frame chip scale pa ckage (lfcsp) . vcm decouple t he vcm pin to ground with a 0.1 f capacitor . reference decoupling externally bypass t he vref pin to ground with a low esr, 1.0 f capacitor in parallel with a low esr, 0.1 f ceramic capacitor. spi port when the full dynamic performance of the converter is required, do not activate t he spi port. because the sclk, csb , and sdio signals are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on - board s pi bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9656 to keep these signals from transitioning at th e converter input pins during critical sampling periods. rev. 0 | page 42 of 44 free datasheet http://
data sheet AD9656 o utline d imensions figure 71 . 56 - lead lead frame chip scale package [lfcsp_ w q] 8 mm 8 mm body, very very thin quad (cp - 56 - 9) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD9656 bcpz - 125 ?4 0c to +85c 56 - lead lead frame chip scale package [lfcsp_ w q] cp -56 -9 ad9 656 bcpzrl7 - 125 ?4 0c to +85c 56 - lead lead frame chip scale package [lfcsp_ w q] cp -56 -9 AD9656 ebz ?4 0c to +85c evaluation board 1 z = rohs compliant part. 0.50 bsc pin 1 indic a t or pin 1 indic a t or * 6.70 6.60 sq 6.50 0.45 0.40 0.35 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.203 ref coplanarity 0.08 0.30 0.25 0.18 08-01-2013-b 8.10 8.00 sq 7.90 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.20 min 6.50 ref * compliant to jedec standards mo-220-wlld-5 with exception to exposed pad dimension. 1 56 14 15 43 42 28 29 t op view bottom view exposed pa d pkg-004323 rev. 0 | page 43 of 44 free datasheet http://
AD9656 data sheet notes ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11868 - 0- 12/13(0) rev. 0 | page 44 of 44 free datasheet http://

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